Background

Following the completion of the first digital clock project, I immediately decided to design and construct another one that was to rectify the faults of the initial version. The main fault that stood out out from the first version was the amount the clock deviated from a reference time piece that was respectable in terms of accuracy. Since the main function of a clock is to keep time, this fault needed to be rectified immediately. Size and power consumption came next in mind for this new revision since the migration to smaller and energy conscience products seemed prevalent in the world today. Along with these few mentioned improvements, the second revision also provided a chance to implement a new 12/24 hour function in place of the alarm that was present on the first version. (Who needs two alarm clocks? O_o)

Project Report Organization

This project report is split into five different sections with each section being comprised of a number of pages or maybe just one.

• Page 01: Introduction - You are here
• Page 02: Design - Overall View
• Page 03: Design - Clock and Reset Signal Generation
• Page 04: Design - Seconds and Minutes
• Page 05: Design - Hours and Time Convention Change
• Page 06: Design - The Interconnections Between the Counter Stages
• Page 07: Design - BCD and 7-Segment Decoding/Display
• Page 08: Design - Frequency Modulation
• Page 09: Design - User Input
• Page 10: Design - Layout and Materials
• Page 11: Construction - General Board Layout
• Page 12: Construction - Power, Clock Source, and Reset
• Page 13: Construction - Seconds, Minutes, and Hours
• Page 14: Construction - Decoders and Output
• Page 15: Construction - 7-Segment Board
• Page 16: Evaluation - Pictures 1
• Page 17: Evaluation - Pictures 2
• Page 18: Evaluation - Analysis and Acknowledgments
• Page 19: Information - Schematics, Datasheets, and other items if applicable.

Goals

To improve over the original design, the following changes were proposed:

• Toggle between Standard and Military Time: The alarm function will be removed and in its place, the ability to switch between 12/24 mode will be implemented.
• Smaller Form-factor: The number of boards utilized in this clock will be reduced to one in order to decrease the height of the product. To achieve this requirement, the JK Flip-Flops will be replaced by Modulo-10 counters.
• Lower Power Consumption: This requirement will be fulfilled by migrating over to a CMOS/TTL hybrid setup.
• Increased Accuracy: The clock source of this clock will be much more stable than the first version.
• Aesthetic Design: Diverging from the bland appearance of the initial clock's body, this design will take on a more futuristic presentation by incorporating a body of transparent acrylic.
• BCD Display: LEDs will be implemented on-board to show the time in BCD between the ICs. I did not say how much lower I wanted to decrease my power consumption!

With these proposed changes in mind, the time that was needed to design and construct this new version was much shorter because the essential function of the clock remains largely unchanged and the bulk of work was done during the hiatus from university work that took place between the spring and summer semesters of 2007.

Disclaimer

Although all data has been checked over, mistakes are certainly possible during the design and construction phases of this project. Therefore, before attempting to replicate or borrow ideas, it would be wise to verify the information presented herein by oneself or with a 3rd party who has sufficient knowledge of the material. That being stated, you may notice a few mistakes in the construction pictures that will be corrected later on. I have tried my best to point out such mistakes and have you avoid making the same ones yourself.