Deriving a 1Hz Clock Source

Since the digital clock will only be as precise as the clock signal it is running its counters on, the requirement for selecting a stable and reliable source is very important. Therefore, after sifting around some common crystal based circuits, I decided to purchase a temperature compensated crystal, by Maxim (Dallas Semiconductor), that is capable of outputting a TTL compatible waveform. This selection, though more expensive, provided me with the opportunity to work with a temperature compensated crystal component as well to fulfill the requirement of utilizing a much more stable clock source. The DS32Khz chip was purchased in a 14-pin DIP form to allow for easy prototyping and integration within the final product.

Due to the output of the ASIC being 32.768KHz, I had to use a 15 stage counter to divide the frequency to the target 1 Hz (32.768KHz / 2^15 = 1Hz). Since I was not able to find a single chip 15 stage counter/divider >_<, I decided to use the 74HC4060, a 14-stage counter, coupled with a D-Type Flip-Flop to form the required 15 stages. By feeding the D-Type Flip-Flop's "!Q" to its "D" input, the Flip-Flop will toggle every time on the rising edge of the clock to provide a frequency that is 1/2 its clock input.

Note that there is a tap on Q9 of the 14-stage counter to drive the multiplexers for the 7-segment displays since the 7-segments that have been chosen, covered later on in this report, are wired so that multiplexing is a must to access individual segments. The choice of tapping Q9 or (32.768KHz / 2^9 = 64Hz) lies in the reasoning that the frequency, being output from this pin, allows fast enough strobing so that the human eye is not able to pick up any discrepancy that may arise from switching between two 7-segment displays.

Reset Signal

Since the circuit for the "reset signal" correctly carried out its function on the first digital clock, there was no reason to change it for this version. A simple capacitor, resistor, and inverter/buffer is all that is needed to carry out the function of generating a signal to clear the contents of the counters during power up and stabilization. There are two outputs, one being the actual reset and the other its compliment. This was done in order to supply the reset signal in a dual rail form so that chips that were either active high or low could be accommodated.

This circuit works on the basis that at the moment power is applied, the capacitor will act as a short-circuit and supply the inverter with a logic high. As time progresses from the initial point of applied power, the capacitor will begin charging up to a point that the inverter will interpret the signal on its input pin change from high to low and therefore change its output. The combination of the RC time and the logic threshold of the logic gate will dictate how long the reset signal is held.

When prototyping this circuit, I found that it is best to use a CMOS inverter with a Schmitt trigger input, such as the 74HC14, for more reliable results.