The Modulo-10 Counter

Due to mainly the size constraints presented by the design requirements, the utilization of a single chip multi-stage counter with the ability to parallel load data was of importance. Thus, the 74LS160 Modulo-10 Counter with asynchronous reset was chosen to form the basis of the second, minute, and hour sections. The need for the multi-stage counter to be of the modulo-10 type was because of the realization that the second, minute, and hour sections all needed to have their one's place value reset from 9 to 0 either all the time, for seconds and minutes, or every other time such as the hours.

As further evidence to support the use of a modulo-10 counter, by restricting each section to only being able to output a valid BCD code, I have eliminated the need to design a circuit to convert binary to BCD for use by the 74LS47 BCD to 7-segment Display Decoders.

The timing and state diagram, below, illustrates the normal counting operation that the 74LS160 exhibits. The timing diagram indicates that an increment can only be accomplished on the rising edge of the clock while the stars in the state diagram mean that transition to the next state is only possible if inputs CET, CEP, PE, and MR are all high.

Seconds Section

The seconds section is formed by using two 74LS160 counters that will form the output for the ones place and the tens place. Since there are only 60 seconds in a minute, the modulo-10 counter for the tens place was modified to be a modulo-6 counter by bringing the Once this is activated, the counter will replace the contents of its states with that of what is present on its inputs. The counter's inputs are designated as P0-P3 and A-D in its data sheet and in the proceeding schematics respectively.Parallel Load Enable pin of that counter low(active low) when a certain condition is met. The parallel load signal was conceived by observing the following: that parallel loading is synchronous with the rising edge of the clock and that the conditions to generate the signal must be when the counters output "59" or "0101 1001" with respect to each counter.

In order to minimize the logic needed to generate this parallel load enable signal, I constructed two K-Maps with the knowledge that the counters do not count above "1001". In addition, as shown by the blue "Don't Cares", since the ten's place counter is to only count up to "0101", the logic was further minimized by ignoring any states above that final count.

Since the seconds stage is the initial stage of the clock, this stage does not need to wait for any previous stages to finish counting up to their designated modulus. Thus the inputs, "CEP" and "CET" or "P" and "T" respectively for the first counter of the seconds stage, were tied high to allow that counter to essentially count the clock pulses.

The second counter for the seconds stage, however, must be connected to the first counter in such a way that it only increments once whenever the ones place resets back to zero. This was accomplished by attaching the "ripple count out" of the first counter to the "CEP" and "CET" inputs of the second counter. In this configuration, only when the first counter resets back to 0 is when the second counter is able to increase its own count with respect to the rising edge of the clock.

Note that propagation to the next stage is taken from the parallel load signal, before the inverter, because by preventing the ten's counter from reaching "1001", the "RCO" of that counter was rendered useless.

Minutes Section

The minutes stage of the clock follows in a very similar manner to how the seconds stage was designed with the only key difference is that for any change to occur, the parallel load signal from the previous stage must be active. Therefore, as bulleted below, only two simple changes were needed to the seconds circuit to fulfill the requirements of the minutes stage.

• "CEP" and "CET" for the ones counter must receive input from the previous stage instead of being tied high.
• The "Parallel Load" and "Next Stage" signals must take into account the input from the previous stage be active.