As to what may have been expected during the development of the counting stages, each progressive stage must rely on the previous stages to be at their respective final counts before the stage in question can change. Fulfilling this requirement was done by tieing the count enable inputs of each stage to the previous stage's carry out. In the case of multiple previous stages, all the carry outs were ANDed and then fed into the input of the stage in question.
Interconnect Schematic - Simple huh?
Because the above circuit links the stages together, it was logical to modify this point to where an external clock signal, along with a few control signals, could be injected for manipulating each stage individually. The integration of such a function was relatively straight forward by implementing a way of locking out all the stages, with the exception of the target stage, and applying the clock signal to all the stages.
This setup decreased the amount of gating the clock signal needed to go through had the control for each stage depended upon locking out the clock signal instead of the count enable inputs for each respective counter.
Interconnect Schematic with the Time Setting function
Although the above schematic is the version one that I have used in constructing the final product, continued usage has shown a "bug" associated with it. The problem lies in the fact that if one were to set the hours' section to 12 and then allow the normal counting to continue, the clock may immediately advance one hour. This "bug" is caused by the hours' stage receiving a clock pulse to advance to the next state whenever a switch in the clock source is made while the control signals are still changing. That is, the manual input clock source may be low, but the built-in source was high at the time. If switching would have occurred when both the manual input and built-in sources were low, then the described "bug" would have not occurred.
Solving a problem like this would detail the need to suppress the built-in clock source's pulses until all control lines have electrically settled. To do this, a series of delay units, such as inverters, would have to be inserted into the clock source line feeding the counting stages.