BCD to 7-Segment Decoders

Depending upon one's decision to count in BCD or binary, the design for translating the output of the counters to 7-segment can either be very simple or a pain in the rear. Luckily, I had decided early on to make my counters count in BCD in order to be able to utilize the BCD to 7-Segment decoder chips for reduced chip count. As the schematic below depicts, I went ahead and multiplexed the data lines before feeding them into the decoders to correctly interface with a particular set of 7-segment displays and reduce the amount of wire routing.

The speed at which the multiplexing occurs was determined by picking a frequency that had a period small enough to be undetectable by the human eye and yet slow enough so that the elements of one 7-segment did not blend into the other. This frequency, 64Hz, was derived from the 14-stage counter that was mentioned in the first half of this article.

To the decoders, I then made provisions for providing a method to control the intensity of the 7-segment displays by using the "blanking input" pin of the BCD to 7-segment decoder chips. To this pin, I fed a FM signal that varied in its frequency in relation to the amount of ambient light - this circuit is covered later.

BCD Counting LEDs

Going along with the "cool factor", the BCD output of the counters were buffered and then fed to LEDs that lit up in a BCD counting pattern. The FM method for controlling the intensity of the 7-segment display was employed here as well. Notice that the last chip has an OR-gate attached to one of its output in a weird configuration. This particular portion was included because I had run out of space to construct independent logic for controlling the LED that indicated whether it was AM or PM for standard time.