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Alternating Modulo Counter
( Actually, I would classify counting in prime numbers as exotic O.o ) The ability to alternate between differing modulos is very useful for a variety situations such as designing the hour's section of a digital clock or accessing, in sequential order, memory. The key behind this method is to recognize that one is just embedding one counter inside of another for the purpose of the outside counter keeping track of which modulo the inner counter is counting at. Since the use of differing modulos for the inner counter will result in possibly conflicting logic at the front-end of at least one stage, the implementation of multiplexers will be key.
In order to not complicate matters, it is wise to address each modulo that you want your counter to count in as each separate entity. For example, if you wish to count modulo-10, modulo-3, and then back again, you would need to create a mod-10 and mod-3 counter first. Once both counters have been created, you would then merge them together and then make a mod-2 counter to oversee the the switching between the two counters that you have just created. If instead you had wanted to count in 3 differing modulos, you would then need to have made a mod-3 counter for record keeping.
EXAMPLE:
Create a counter that will alternate back and forth between modulo-10 and modulo-3
The first course of action (besides panicking) is to create two independent counters: a mod-10 and a mod-3. We begin, like before, by finding how many stages will be needed to count to the final count of each mod-n counter.
Four stages are needed for mod-10, and two stages are need for mod-3
For both mod-n counters to coexist with one another, we shall alter the size of the smaller counter so that it matches the size of the largest one. This action will not change the function of the smaller one per se because the extra stages are essentially not used.
Next, the steps for building a mod-2 counter are carried out. This counter will be the one that keeps track as to which modulo the other combined two are counting in for this setup.
After viewing the above, you may ask if we even needed to go through the comparison table. Probably not, but it never hurts to make sure.=p We proceed onward by first laying out a generic mod-16 counter since this it is the maximum modulo our counter can be.
Then the logic for either the mod-3 or mod-10 counters is laid (order does not matter but I will go with mod-10).
I have labeled the logic belonging to the mod-10 counter portion as blue to distinguish it from the green mod-3 portion. The logic to the LSB stage may look weird but recall the optimization made to the mod-25 counter on previous page.
The first thing you may notice is that there is a conflict on the input of the 2nd stage of the counter because both the AND and OR gate must feed into it. The remedy to this is to add a multiplexer that will switch between the two depending on what state the external mod-2 counter is in (Yes, it is pink). I have added, as well, the final count logic for each counter and left the outputs dangling because it is important that the final count lines be gated so that they do not interfere with the current count if needed.
Since there is a MUX in front of the second stage, the final counts that feed into those stages need not be gated. Though, the one in front of the first stage needs to be addressed because of no MUX. Using the same lockout methodology as the logic feeding the stages, we will lockout the final count signal when not needed so we use an INV-AND.
Last item involves adding the mod-2 counter to the mix. This stage may be a bit more difficult to understand because it is triggered by either mod-10's final count and, as long as it is in a certain state, mod-3's final count. This can be seen by tracing the feed from the input of the brown AND gate to the output of the green AND gate. Note that the green AND gate is controlled, in part, by the very flip flop that it eventually feeds into through those two AND gates. The cyclic pathway can be better understood by imagining that the flip flop can only reset the count back to zero only if it is in a certain state and receives a certain final count.
We are finally done! As you may have surmised, there are a plethora of scenarios in which present a far more complex challenge than what is offered here but that is for another tutorial. Now I am off to make a multi modulo 2,3,4,...64 selectable counter. >.>
Waveform simulation result of this circuit
